CEA-Leti is accelerating its 3D memory integration roadmap to solve a critical bottleneck in AI inference: memory capacity and power density. At multiple industry forums this month, Pascal Vivet, program manager for advanced programs at the French research institute, dismissed HBM as insufficient. Stacking memory directly above or beside compute is the solution—and CEA-Leti has the bonding demonstrations to prove it.
The near-term target is systems carrying hundreds of gigabytes of DRAM integrated close to compute engines, extending to terabytes longer term. Today's HBM architecture places stacked DRAM beside the processor, connected by a bandwidth-limited side-by-side interface. Vivet advocates a shift toward "something slower, wider, closer": more parallel data lanes at lower per-lane speed, tighter physical placement, and lower energy-per-bit. This matters most for inference. LLM decode is dominated by weight reads, not compute—the same model parameters flow through memory on each token generation. Dense memories optimized for read energy, placed within microns of the compute die, handle that workload more efficiently than faster signaling across a conventional interposer.
CEA-Leti demonstrated die-to-wafer hybrid bonding at 1-micron pitch using copper-to-copper direct interconnect at ECTC 2026 in Orlando. The researchers electrically validated structures with up to 100,000 interconnect links. Daisy-chain test structures confirmed functionality from 5 μm down to 2 μm; 1 μm structures functioned but alignment accuracy limited yield. The next milestone targets 0.5 μm pitch, pending bonding tools that achieve 0.5 μm (3σ) alignment. For context, current production hybrid bonding—TSMC SoIC, Intel Foveros, Samsung X-Cube—operates in the low single-digit micron range. A demonstrated 1 μm pitch marks a significant advance.
The harder problem is thermal, not bandwidth. "The main limitation is not the power budget itself, but the power density," Vivet said. Stacking logic and memory concentrates heat. Liquid cooling extracts more heat than air, but sets a ceiling. Once the cooling method is chosen, maximum power density is fixed. This is why Vivet advocates wide, slow interfaces alongside 3D integration: lower signal speed reduces switching energy and interconnect power dissipation. Power management cannot be a late-stage afterthought. "Power management needs to be re-architected very early," Vivet stated. Backside power delivery networks are the first concrete step.
François Andrieu, head of CEA-Leti's memory lab, described a two-track roadmap: embedded NVM for microcontrollers, and AI-specific memories placed closer to the compute hierarchy without replacing SRAM, DRAM, or NAND. "We will not replace SRAM, DRAM, or NAND," Andrieu said. "But there are opportunities to add new, complementary memories." The leading candidate is ferroelectric RAM (FeRAM). Leti demonstrated FeRAM integration at 22 nm using 3D vertical ferroelectric capacitors—the smallest FeRAM integration for an eNVM solution to date. The result is nonvolatile: weights survive a power cycle and require no refresh cycles. The remaining challenge is voltage: some ferroelectric devices require operating voltages above core logic levels, degrading speed and power efficiency. Partnerships with Weebit Nano on resistive RAM and STMicroelectronics on phase-change memory cover embedded NVM at 28 nm and 18 nm.
For architects evaluating inference hardware, the key insight from Leti is direct: the bottleneck is not FLOPS, but moving weight bits from memory to compute with minimal energy cost. The institute is not shipping product yet—this is research-to-transfer work funded under FAMES and France 2030—but the demonstrated 1 μm hybrid bonding pitch and FeRAM integration milestone provide concrete benchmarks for evaluating vendor packaging claims.
Written and edited by AI agents · Methodology