Token prices have fallen orders of magnitude since 2022. The reflexive assumption is that model efficiency improvements—smaller parameter counts, better quantization, distillation—will push them lower still. That assumption ignores the supply chain. According to SemiAnalysis research presented at QCon AI, the rate-limiting variable on inference cost floors is not how many operations a model requires per token. It is how many wafers TSMC can produce per quarter.
TSMC's N3 node is the current chokepoint. Every major accelerator roadmap has converged on it: Nvidia's Rubin, Broadcom custom ASICs, Google's TPUv7, AMD's MI series, Annapurna, MediaTek. SemiAnalysis models AI-related demand—accelerators, host CPUs, networking silicon—consuming just under 60% of all N3 output in 2026. By 2027, that figure reaches 86%, nearly squeezing out smartphone and consumer PC chips from the same node. N3 utilization is expected to exceed 100% in H2 2026. A 3nm wafer costs $19,500–$21,000 at commercial pricing; 2nm wafers cost above $30,000—a 50% premium. TSMC has announced price increases for four consecutive years beginning in 2026, with 3nm rising approximately 3% and advanced nodes potentially reaching 10%.
| Node | Wafer Price (Commercial) | AI Share of Output — 2026 | AI Share of Output — 2027 | TSMC Annual Price Increase |
|---|---|---|---|---|
| 3nm (N3) | $19,500 – $21,000 | ~60% | ~86% | ~3% |
| 2nm | >$30,000 (~50% premium over N3) | — | — | Up to ~10% |
The packaging layer compounds the constraint. Even a flawlessly fabricated wafer cannot ship as a functional AI accelerator without CoWoS—TSMC's Chip-on-Wafer-on-Substrate 2.5D process that bonds a GPU or accelerator die to stacks of high-bandwidth memory on a silicon interposer. TSMC CEO C.C. Wei has stated CoWoS is sold out through 2026. TSMC is scaling CoWoS output roughly tenfold from late 2023, targeting 120,000 to 130,000 wafers per month by end of 2026—an expansion fully consumed before delivery. Lead times on CoWoS slots run 52–78 weeks. Nvidia has reserved the majority of available CoWoS allocation. Memory and packaging together represent 60–70% of AI accelerator COGS; logic silicon is no longer the dominant cost driver.
The effect on inference pricing is direct. H100 1-year rental contract prices rose 40% from their October 2025 trough. Memory prices increased 6× in the past year; DRAM prices are expected to double or triple again, with capacity growing only 20–30% annually. New fabs, triggered by late-2025 demand signals, will not deliver meaningful supply until late 2027 or 2028. Anthropic's gross margins moved from roughly 30% to at least 72%, not by cutting costs but by rationing access: the company slashed usage and rate limits because demand outstrips capacity. SemiAnalysis tracked its own token spend climbing from approximately $10,000 per year in late 2023 to $7 million annualized by early 2025—28% of its $25 million salary base.
Model efficiency matters. Reasoning models that deliver better outputs per token shift unit economics. But they do not unlock additional wafer starts. They do not shorten the 52-to-78-week CoWoS queue. They do not alter TSMC's four-year pricing trajectory. TSMC capex only exceeded its previous historical peak in 2025, despite the AI buildout beginning in late 2022—a multi-year lag that explains why supply has not kept pace with demand. SemiAnalysis co-founder Dylan Patel projects TSMC reaching a $100 billion capex year by 2028, with meaningful capacity relief arriving no earlier than late 2027.
For architects building multi-year inference stacks: model efficiency improvements will compress the compute cost component. The floor on token prices is set by TSMC's node pricing schedule, CoWoS allocation queues, and HBM spot markets—none of which track model parameter counts. Build inference cost models around fab economics first, efficiency curves second.