Samsung laid out a full-stack memory roadmap at this week's Future of Memory and Storage Summit in Santa Clara, spanning HBM4E, HBM5, and two concept architectures—zHBM and zNAND-O—designed to support 10× more AI token throughput by 2030. Leno Park, VP of flash solutions at Samsung Electronics, grounded the roadmap in a concrete problem: AI clusters today support roughly 100 tokens per second per user; Samsung is engineering for 1,000 tokens per second by 2030.
HBM4E is the nearest deliverable. Samsung shipped samples in May and confirmed active evaluation by major ecosystem partners. The product uses a 4 nm logic base die, increases through-silicon via (TSV) count by approximately 4×, and deploys advanced packaging with more than 300,000 microbumps at tighter pitches. Result: 4 TB/s bandwidth and 64 GB capacity in a single 16-high stack, with I/O speeds of 16 Gbps per pin—more than 20% faster than HBM4. To manage thermal concentration in dense stacks, Samsung added a heat pipe block—a "chimney" placed directly over hot spots.
| Generation | Base Die Process | Bandwidth | Capacity | I/O Speed | Key Technology |
|---|---|---|---|---|---|
| HBM4E | 4 nm | 4 TB/s | 64 GB (16-high stack) | 16 Gbps/pin (>20% faster than HBM4) | TSV count ×4; 300K+ microbumps; heat-pipe chimney for hot-spot cooling |
| HBM5 | 2 nm (GAA) | — | — | — | Gate-all-around transistors; shortened interposer channels for better I/O signaling |
| zHBM | TBD (co-design) | 8× HBM5 (claimed) | >10× HBM5 density (claimed) | — | Accelerator stacked directly on HBM; 3D unified structure; 3× energy efficiency; <50% thermal resistance vs. HBM5 |
HBM5 shifts the base die to a 2 nm process using gate-all-around (GAA) transistor technology. Samsung is also shortening interposer channel lengths to improve I/O signaling between base die and accelerator. The node shrink targets another bandwidth-per-watt step before architecture changes with zHBM.
zHBM collapses the 2.5D side-by-side layout of current HBM integration. The AI accelerator sits directly above the HBM stack as a unified 3D structure, cutting physical distance between processor and memory. Samsung claims the next-generation interface could deliver 8× the performance of HBM5, more than 10× memory density, 3× energy efficiency, and less than half the thermal resistance. Reaching those numbers requires close co-design with accelerator partners—limiting adoption to vendors willing to share die-level design data and coordinate packaging.
Samsung also announced the V10 BV-NAND, its 10th-generation TLC V-NAND, with 400 layers, an 11% lateral shrink, and 58% higher memory density versus the prior generation. It introduced LPDDR5X-PIM, the first LPDDR memory with processing-in-memory capability, offloading selected data operations into memory to reduce memory-compute round-trips. The PCIe Gen6 PM1763 SSD entered mass production in July 2026 for AI data-center checkpoint and dataset I/O.
| Product | Type | Key Specifications | Status |
|---|---|---|---|
| V10 BV-NAND | 10th-gen TLC V-NAND | 400 layers; 11% lateral shrink; 58% higher memory density vs. prior gen | Announced |
| LPDDR5X-PIM | LPDDR with processing-in-memory | First LPDDR-class PIM; offloads data operations into memory to cut memory-compute round-trips | Announced |
| PCIe Gen6 PM1763 SSD | Data-center NVMe SSD | PCIe Gen6; targets AI checkpoint and dataset I/O workloads | Mass production — July 2026 |
Samsung's HBM revenue outlook underscores urgency: HBM sales will more than triple in 2026 versus 2025, and reach 50% of total DRAM revenue by 2030. After 2029, incremental speed bumps won't close the gap. The structural question is whether co-designed 3D integration like zHBM ships on time and at yields that make it usable for procurement decisions, not just roadmap slides. HBM4E at 4 TB/s and 64 GB per stack is available for evaluation now; HBM5 and zHBM remain co-design items—factor that uncertainty into any cluster build beyond 2027.