Synopsys CXL 4.0 IP Hits 128 GT/s Bandwidth with Integrated Security

Synopsys has announced the industry's first complete CXL 4.0 IP suite: a controller, IDE security module, PCIe 7.0 physical layer, and verification IP. The announcement completes a set that began in December 2025 with the first commercially available CXL 4.0 VIP. For hardware architects designing AI SoCs, CXL 4.0 doubles link bandwidth to 128 GT/s over CXL 3.x, and IP supply is only now catching up.

The core advantage in CXL 4.0 is port bundling. CXL and PCIe cap at 16 lanes per port. CXL 4.0 lets designers combine multiple x16 links into a single logical port. Four x16 links deliver more than 2 TB/s of aggregate bandwidth (bidirectional, TX + RX combined). Eight links exceed 4 TB/s. Proprietary interconnects have long claimed aggregate bandwidth as an edge over standard alternatives. Bundled ports close that gap without abandoning the PCIe physical layer. CXL 4.0 adds support for up to four retimers per link—necessary at 128 GT/s because higher data rates reduce channel distance—and a 256-byte latency-optimized FLIT that increases payload efficiency per cycle.

The Synopsys PHY is a PCIe 7.0 SerDes hardened for 5nm through 2nm process nodes. Load-to-use latency on CXL.mem sits below 200 nanoseconds. Synopsys claims CXL-based key-value cache offload delivers 3–6× the performance of SSD-based alternatives at 128 GT/s (vendor-supplied figure; no independent benchmark methodology disclosed). Rack-scale memory pools can exceed 100 TB. The company projects 50–100% inference cost reduction depending on configuration. KV-cache latency and capacity constrain long-context LLM inference. DRAM-speed coherent memory directly addresses both.

The unified controller covers CXL 1.x, 2.0, 3.x, and 4.0 under a single license and includes PCIe 7.0 fallback without a separate purchase. CXL 2.0 is already in volume production. CXL 3.x is only beginning to ship at scale. Design teams need to support multiple generations of installed infrastructure. A unified controller provides one integration path instead of maintaining parallel IP blocks.

Synopsys's IDE modules implement AES-GCM encryption and authentication with zero-cycle latency overhead in skid mode for both CXL.cache and CXL.mem, with TSP/TDISP support and FIPS 140-3 readiness. TDISP support targets multi-tenant hyperscaler SoCs where virtual machine isolation across coherent memory requires hardware-enforced authentication. Ron Loman, product marketing manager for PCIe and CXL IP at Synopsys, said: "With PCIe 7 and CXL 4, we're seeing an extremely high rate of adoption with IDE and the security aspect. People realize you have to have the security in place and they're planning for it."

Ecosystem maturity is the harder constraint. A fully realized CXL-based disaggregated memory system requires compatible CPUs, accelerators, SSDs, memory controllers, switches, and software stacks. Synopsys has shipped more than 170 CXL controllers and PHYs to date, against more than 3,800 PCIe design wins. The gap reflects how early the CXL volume ramp remains. Synopsys cites a Goldman Sachs Research projection that global AI token consumption will grow 24× by 2030, reaching roughly 120 quadrillion tokens per month. The CXL 4.0 VIP ships with migration paths from CXL 3.0 and PCIe 7.0 because standards validation becomes a late-stage bottleneck when the ecosystem is thin.

CXL 4.0 IP is now available from the dominant IP vendor at sub-200ns latency and 128 GT/s link speed, with security built in. The bottleneck has moved to the rest of the stack.