TSMC is sitting on approximately $1 billion in fabricated A20 Pro processors awaiting DRAM supplies before they can be packaged, creating a critical bottleneck just six weeks before the iPhone 18 Pro launch. The A20 Pro is Apple's first chip on TSMC's N2 process, and uses a new Wafer-Level Multi-Chip Module (WMCM) process that integrates DRAM and processor at the wafer level—meaning packaging cannot proceed without memory arriving simultaneously. N2 production yields are good and volumes are strong; the constraint is entirely upstream DRAM supply.
Apple sources DRAM primarily from Micron, with smaller volumes from SK Hynix and Samsung, but all three major memory suppliers have redirected capacity toward High-Bandwidth Memory for AI accelerators, which commands far higher per-wafer margins than the LPDDR5X Apple needs. Apple attempted to qualify China's CXMT as a fourth source, but after navigating geopolitical complications, CXMT's capacity is already committed to Chinese buyers at competitive pricing.
According to sources close to the supply chain, Apple and its assemblers remain confident they can meet initial iPhone 18 Pro demand, but warn that online wait times could stretch quickly and retail inventory may dry up if the shortage persists. TSMC's recent earnings revealed inventory days climbed seven days to 87 in Q2, primarily attributed to the N2 ramp, signaling wafers piling up downstream. Final assembly at Foxconn and BYD in China could compress production schedules, putting some iPhone 18 Pro models at risk of scarcity in early weeks.
For architects: this is a real-time supply-chain crisis at the intersection of semiconductor manufacturing and packaging innovation. Apple's aggressive shift to wafer-level memory integration leaves zero flexibility for memory delays, and it exposes a hard constraint—the oligopoly of DRAM suppliers and their strategic reallocation of wafer capacity to AI. This pattern will ripple across any vendor dependent on leading-edge process nodes paired with high-performance memory.