AMD Confirms Low-Power Cores in Future Zen Processors, Following Intel's Heterogeneous Architecture Model

AMD submitted Linux kernel patches on June 30 confirming support for a new class of low-power CPU cores in upcoming heterogeneous processors, signaling a shift toward the "big.little" design pattern Intel has deployed in recent generations. The patch introduces a third core classification—alongside existing Performance and Efficiency cores—optimized specifically for idle and background tasks where power consumption matters more than throughput. According to AMD engineer Vishal Badole, these cores are designed to minimize energy draw during non-critical workloads, improving battery life in mobile devices and reducing data-center idle power.

AMD's approach mirrors Intel's strategy in Meteor Lake and Nova Lake mobile/desktop processors, where lower-power SoC-tile cores handle background tasks. However, AMD's implementation differs: it reuses the same Zen microarchitecture (optimized via die layout and clocking) rather than creating entirely separate silicon, simplifying software development but potentially sacrificing power efficiency gains versus Intel's heterogeneous cores. The kernel patch enables Linux to distinguish between all three core types and route tasks appropriately via existing AMD performance management mechanisms; no new scheduling logic is exposed.

For platform architects and OEM teams, this is a 12- to 18-month heads-up on refresh cycles. Low-power cores promise measurable gains for server idle power (material at fleet scale) and laptop battery endurance (competitive feature versus Intel). Expect the first retail parts with Zen LP cores to appear alongside Zen 6 desktop/mobile launches (likely H2 2026–Q1 2027). Infrastructure teams should begin modeling TCO impact of heterogeneous core scheduling; enterprises may see 5–15% idle power reduction on workloads with predictable background traffic patterns.