AMD X100 SoC lineup targets embedded physical AI; Strix Halo cores + 50 TOPS XDNA 2 NPU for robotics

AMD unveiled the X100 series of processors for embedded physical AI applications, bringing Strix Halo APU architecture into robotics and edge deployments with a 10-year lifecycle. The lineup spans three SKUs: the X199 (16 Zen 5 cores, 40 RDNA 3.5 CUs), X188 (12 cores, 32 CUs), and X168 (8 cores, 32 CUs), each with up to 128 GB unified memory, 50 TOPS XDNA 2 NPU, and configurable TDP between 45W and 120W for -40°C to +105°C operations.

AMD benchmarked the X199 against Intel's Core Ultra X7 358H, claiming 1.2X GeekBench 6.1, 1.3X PassMark, 1.5X SPECrate integer workload leads, and 1.4X time-to-first-token (TTFT) plus 3.5X tokens-per-second on Llama-bench at 45W TDP. However, AMD tested against Intel at 30W (with projected scaling), creating apples-to-oranges variance that reviewers should salt accordingly.

AMD is shipping the X100 as a Kria System on Module (COM-HPC form factor) alongside a robotics developer platform combining the Kria X100 SOM with Spartan UltraScale+ FPGA baseboard, specialized camera/industrial networking, and sensor interconnects. The developer box is in early access now; full production ships Q4 2026. AMD also claims its HIPIFY tool can now auto-port 70–80% of CUDA code effort to AMD HIP.

For robotics and autonomous-vehicle architects, the X100's integrated NPU, CPU, and GPU on a single SoC with decade-long lifecycle support addresses latency and power constraints that distributed Nvidia Jetson solutions don't. The tradeoff: smaller developer ecosystem and unproven long-term support compared to x86 and ARM incumbents.