CEA-Leti 3D stacking roadmap tackles AI memory bottleneck with sub-micron interconnects

CEA-Leti, France's microelectronics research institute, is pushing an aggressive 3D integration and chiplet roadmap to address AI systems' collision with memory bandwidth and power-density walls. Program manager Pascal Vivet outlined a shift from today's high-bandwidth memory (HBM) architectures to 'wider, slower, closer' memory interfaces—stacking DRAM directly above or inches from compute engines using ultra-dense interconnects. The goal: hundreds of gigabytes to terabytes of memory integrated tightly with processors to feed inference workloads that are I/O-bound rather than compute-bound.

Leti's toolbox spans 10-micron to sub-1-micron pitches, including die-to-wafer and wafer-to-wafer hybrid bonding demonstrated at 1-micron pitch and targeted at 200 nm. The key insight is that closer integration reduces data-movement energy—critical for inference—but concentrates heat. Power density (not total power) becomes the limiting constraint; liquid cooling in data centers sets a ceiling, while edge-AI systems in cars and drones face different thermal budgets.

For architects, this signals a pivot: as frontier model weights saturate DRAM, the next generation of AI hardware will trade pure bandwidth for placement, lower-energy wide buses, and chiplet modularity. This roadmap implicitly supports both the 'scale up' and 'open chiplet' camps—showing that tighter memory coupling beats more bandwidth-per-dollar in inference, favoring integrated designs over monolithic dies.