Chinese university builds 3D chip design tool for Huawei LogicFolding architecture

Peking University developed a 3D chip design tool tailored to Huawei's LogicFolding architecture, delivering gains in performance density and thermal management. The toolchain release suggests Chinese semiconductor development is moving past node matching into custom 3D integration—a key lever for closing the design-tool gap with TSMC/Samsung.

For supply-chain strategists, this is a marker that China is building indigenous CAD/EDA and physics-simulation ecosystems. Open-source chip design tooling, combined with vertical integration (fab + design), could shift the cost baseline for custom accelerators.