Chips go vertical; metrology struggles to keep up, EE Times warns

EE Times analysis shows that as chipmakers move to 3D vertical stacking (chiplets, advanced packaging, gate-all-around transistors), traditional metrology tools and processes are hitting scale limits. Measurement and inspection vendors must retool hardware and software to track sub-nanometer features in three dimensions.

The bottleneck threatens fab productivity and yield as design complexity outpaces the ability to measure and control it—a supply-chain problem that could tighten advanced-node capacity and raise costs for AI accelerator and GPU manufacturers.