DAC 2026: Microsoft Artour Levin keynotes EDA bottlenecks at AI accelerator scale; hardware-software boundaries become the pain point

The Design Automation Conference 2026 (July 26–29, Long Beach) is previewing a shift in EDA (electronic design automation) methodology driven by AI accelerator complexity. Microsoft's Artour Levin, VP of AI Silicon Engineering, will deliver a keynote on Wednesday titled 'EDA Opportunities in Building High Performance AI Accelerators,' framing the core problem: as accelerators scale from chips to full systems, hard problems increasingly emerge at boundaries—between compute, memory, interconnect, and software behavior—exactly where traditional EDA silos were not built to operate.

The conference's Engineering Track spans 15 sessions with ~90 peer-reviewed presentations on what worked and broke in 2026 silicon. Notable talks include Intel's Lalitha Immaneni on heterogeneous integration, IBM Research's Huiming Bu on 7nm-to-7Å process evolution, and Qualcomm EVP Baaziz Achour on 'Design Automation for Emerging AI: From AI Chips to Data Center.' Additionally, Tuesday's 'AI-Accelerated IP Libraries' session highlights how standard-cell design itself is now using ML: AI-driven transistor-level sizing generates 2x power and timing improvements on real industrial silicon while staying compatible with legacy EDA flows.

For architects: DAC 2026 signals that point-tool optimization (what traditional EDA does) has hit diminishing returns for AI silicon. The next frontier is system-level holistic verification and co-simulation—bridging logic, memory, interconnect, power, thermal, package, and software in a unified design loop. This is a multi-year shift in how chip design organizations staff and tool selection.