IBM and Lam Research team up on sub-1nm logic with High-NA EUV for 2030s production

IBM and Lam Research announced a five-year collaboration to develop materials, manufacturing processes, and High-NA EUV lithography technologies for sub-1nm logic devices. The work will occur at IBM's Albany NanoTech Complex using Lam's equipment including Aether dry resist, Kiyo/Akara etch tools, and STRIKER/ALTUS deposition tools. This builds on over a decade of partnership that produced IBM's 2nm breakthrough in 2021 and nanosheet transistor architectures.

The collaboration targets High-NA EUV dry resist process integration and atomic-scale precision in patterning, etch, and deposition. Sub-1nm process work starting in 2026 is unlikely to reach volume manufacturing before the early 2030s. The focus is on new interconnect architectures including nanosheets, nanostacks, and backside power delivery—techniques that enable continued scaling when conventional lateral shrinking encounters physics limits.

IBM, having exited chip manufacturing decades ago, maintains its Albany facility as a process development site whose innovations flow to production foundries like TSMC. Lam Research brings materials expertise (dry resist technology, Aether adoption by memory makers in 2025) and equipment integration skills. ASML's High-NA EUV lithography (0.55 numerical aperture vs. 0.33 for Low-NA) is critical enabler: it improves resolution and allows direct-print patterning instead of multi-patterning workarounds.

For architects, this signals the next competitive frontier: once 2nm reaches maturity (TSMC now in volume production), the race shifts to sub-2nm with High-NA EUV, 3D transistor designs, and new materials. IBM and Lam's public research roadmap will inform foundry adoption timelines. The collaboration positions Lam as the materials-and-equipment partner for post-Low-NA EUV nodes, critical as foundries diversify away from legacy multi-patterning costs.