IBM unveiled the world's first sub-1 nanometer (0.7-nm) chip technology, featuring a revolutionary nanostack 3D transistor architecture that packs nearly 100 billion transistors onto a chip the size of a fingernail—nearly twice the density of IBM's 2nm chip unveiled in 2021.
Published technical results project the new chip to offer up to 50% more performance or 70% greater energy efficiency than IBM's 2nm node chips, supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices. IBM's VP of global semiconductor R&D said the nanostack platform can enable future scaling for another decade with production targeted within five years.
IBM researchers demonstrated that the nanostack architecture provides 40% scaling improvement in SRAM—a critical unlock for AI chips that must handle bandwidth-intensive workloads while reducing latency and power consumption. IBM estimates AI accelerators using 7 angstrom (sub-1nm) technology could deliver approximately 7,000 TOPS (trillions of operations per second), compared to today's ~1,500 TOPS from current leading accelerators.
The advancement matters for architects because it extends Moore's Law into the atomic-scale regime and addresses the memory wall limiting AI inference efficiency—a cornerstone problem as capex scales.