LPDDR and SOCAMM memory gain traction in AI data centers as HBM supply tightens

EE Times reports that low-power DRAM (LPDDR) and small-outline compression-attached memory module (SOCAMM) are gaining adoption in AI data centers as high-bandwidth memory (HBM) supply becomes constrained and inference workloads replace training as the dominant compute pattern. LPDDR, originally designed for smartphones, and SOCAMM, a compact form factor, offer significant power-efficiency advantages: SOCAMM consumes one-third the power of standard DDR5 RDIMM while enabling higher memory per socket and density.

Micron's recently launched 256GB SOCAMM is designed for dense server builds and offloads KV-cache from HBM, improving performance-per-watt for inference and production AI workloads. Praveen Vaidyanathan, VP of Cloud Memory Products at Micron, told EE Times: "The opportunity for low-power DRAM in the data center is very high. Emerging workloads such as mixture-of-experts models, multimodal AI, and agentic systems are increasing demand for memory close to compute, and long context windows are becoming more common."

The memory hierarchy is reshuffling: Micron positions hot KV cache in HBM, warm KV cache in low-power DRAM, and cold KV cache in fast storage. Rambus has similarly announced SOCAMM2, an LPDDR-based server module chipset for future AI systems. Jim Handy, principal analyst with Objective Analysis, notes that hyperscale operators are willing to pay for efficiency because "performance per watt is a decisive factor, especially when AI is consuming a large share of data center spending."

For data center architects, the adoption of LPDDR and SOCAMM signals a shift away from HBM-only inference strategies: a tiered memory approach balances capacity, latency, and total-cost-of-ownership as inference becomes the dominant AI workload. This architectural change affects GPU procurement, memory module sourcing, and cooling/power budgets across the stack.