MIPS, now a GlobalFoundries company, has made the MIPS S8200 RISC-V NPU available for sampling to lead customers developing autonomous edge robotics, transportation, and embedded platforms. The S8200 tightly couples RISC-V application cores with AI inference engines, enabling low-latency data exchange between general-purpose processing and transformer/CNN model execution, with first-silicon reference platforms expected in 2027.
In parallel, MIPS and German semiconductor firm Inova Semiconductors unveiled a robotics control reference platform combining MIPS' RISC-V processors with Inova's high-speed APXpress data interfaces into a unified sense-think-act-communicate SoC. The platform targets humanoid and advanced robotics, reducing form factor, power, and BOM cost. Developers gain early access via MIPS Atlas Explorer, a simulation environment for hardware-software co-design before silicon availability.
The broader ecosystem signals a structural shift: RISC-V is becoming the connective tissue for edge AI and physical systems. SiFive's 2nd Gen Intelligence family (X160/X180 for far-edge IoT, X280/X390 for higher performance) targets autonomous robotics and automotive; Infineon and other legacy players are adding RISC-V roadmaps for SDVs and industrial control. MIPS estimates RISC-V edge AI processors will reach 129 million units by 2030.
For practitioners shipping embodied AI, the S8200 availability matters because it eliminates the CPU-to-accelerator boundary that introduces latency, while the reference platform blueprints (zonal architecture, deterministic connectivity, functional safety support) reduce prototyping risk. Open ISA customization avoids vendor lock-in that proprietary accelerators impose.