NVIDIA deploys Vera CPU across EDA design workflows; Cadence & Synopsys show 1.5x gains

NVIDIA announced it is deploying its Vera CPU—an 88-core Olympus-based custom processor with high-efficiency LPDDR5X memory and second-generation Scalable Coherent Fabric—across EDA (electronic design automation) workflows used to design its next-generation CPUs and GPUs. Vera is optimized for simulation, verification, and implementation stages of chip design, where traditional CPU performance remains critical despite GPU acceleration of other design tasks. Early testing with Cadence Jasper (formal verification) and Synopsys VCS (functional simulation) showed up to 1.5x higher performance on selected production-class workloads.

Verification and implementation are the design bottleneck: before a chip reaches manufacturing, engineers run thousands of validation iterations. Logic simulation, formal verification, and digital implementation depend on single-core performance, memory subsystem efficiency, and sustained throughput—the inverse of GPU-heavy workloads. By deploying Vera in-house, NVIDIA is shortening design cycles for its own processors while validating the architecture for future licensees. Cadence and Synopsys are profiling Vera further for broader software optimization and system-level tuning to extend performance gains across more workflows.

For chip architects and NVIDIA customers, this is a productivity signal: tapeout schedules depend on verification throughput, and a 1.5x speedup in logic simulation and formal verification reduces design-iteration time materially. NVIDIA plans to follow Vera with Rosa (powered by the Rigel core), creating a continuous feedback loop between silicon design and CPU architecture. The move reflects how modern chip design is no longer monolithic GPU compute—different stages require different hardware, and CPU performance remains a bottleneck worth fixing separately.