Christopher Domas, a hardware researcher, launched the CPU Deoptimization leaderboard to measure single x86 instructions with the highest latency—the inverse of traditional instruction optimization. The record holder, fxrstor64 (a SIMD state-restore instruction), takes 62 seconds (198 billion CPU cycles) to execute under specific conditions. To achieve this, Domas first used a custom tool to locate a high-latency area in the PCIe fabric, then forced the CPU to load a 512-byte state from Memory-Mapped I/O (MMIO) at maximum slowness, queuing the operation behind frivolous MMIO reads to starve the PCIe root complex.
The methodology reveals CPU behavior under pathological conditions. Domas' approach pairs the state restore with multiple 4-byte reads from high-latency MMIO registers, overwhelming the PCIe root complex and forcing serialization. The experiment highlights how memory hierarchy, I/O subsystem contention, and register-file pressure can compound to create worst-case latencies orders of magnitude higher than spec sheets suggest. All timings are normalized by CPU base clock; platforms were run without hardware modifications or software interruptions.
Domas plans to expand with ARM and RISC-V leaderboards. The project serves an educational purpose: while optimization research dominates academic and industrial focus, understanding pathological instruction behavior helps chip designers identify bottlenecks and software engineers recognize scenarios where performance-critical code might stall unexpectedly. The xrstor64 record could be extended further using Intel Sapphire Rapids' AMX instructions, which scale the state area from 512 bytes to 8KB—potentially causing trillion-cycle hangs.
For architects and hardware researchers, this is a novel contribution to the instruction set benchmarking landscape. It exposes the gap between peak specification and real-world latency under pathological load, relevant for understanding cache coherency, I/O back-pressure, and cross-domain contention in modern CPUs.