TSMC is developing an advanced chip-packaging technology internally called "EMIB-like" in partnership with Taiwan-based Kinsus Interconnect Technology, responding directly to Intel's growing threat to its near-monopoly on AI accelerator packaging. The move signals a recognition that Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology—which uses small silicon bridges to connect chiplets at lower cost and higher efficiency than TSMC's conventional Chip-on-Wafer-on-Substrate (CoWoS)—is winning major customers and pose strategic risk. TSMC's CoWoS lines are fully booked through 2026 and into 2027, with lead times stretching to 52–78 weeks, leaving customers no choice but to evaluate alternatives.
Intel's EMIB-T variant reached a 98% yield rate in mid-July 2026—achieving manufacturing parity with TSMC's mature CoWoS process for the first time. Backed by that validation, Intel has secured major wins: Google is placing an order to package over 3 million custom TPUs in 2028 using EMIB-T, Amazon is using it for Trainium 3, and MediaTek has adopted a dual-sourcing strategy (TSMC CoWoS for training chips, Intel EMIB-T for inference). Most strategically, Nvidia is evaluating EMIB-T for its next-generation Feynman GPU, with industry estimates suggesting a 25%/75% split between Intel and TSMC packaging volume.
For operators: Packaging has become the bottleneck in AI infrastructure deployment, not process nodes. TSMC's EMIB-like project represents a defensive play to retain volume but risks conceding margin advantage if Intel's lower cost structure is validated at scale. Watch: yield maturation of EMIB-T in 2027, Nvidia's final packaging split for Feynman (due 2028), and whether TSMC's CoWoS relief measures (CoPoS glass-substrate roadmap, CoWoP pilots) reach volume production on schedule to re-establish supply parity.