TSMC, imec, ASML demonstrate 2D transistors at 50nm pitch on 300mm wafers

TSMC, imec, and ASML have jointly demonstrated complementary metal-oxide-semiconductor (CMOS) devices using atomically thin 2D transition metal dichalcogenides (TMDs) at a 50nm contacted poly pitch on a 300mm wafer—the tightest pitch yet achieved for 2D devices and within range of today's leading-edge silicon. The trio presented results this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits.

The n-channel transistors use molybdenum disulfide (MoS2) and the p-channel use tungsten diselenide (WSe2) or tungsten disulfide (WS2), printed with a single EUV exposure to produce channel lengths as short as 28nm. Ninety-four percent of the integrated transistors switched correctly with an on/off current ratio above 100,000. The key innovation is a 'reverse' thin-film-transistor flow: the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, avoiding contact resistance bottlenecks that have historically throttled current delivery in scaled 2D devices.

This milestone demonstrates the path toward post-silicon CMOS scaling. However, significant gaps remain: the integration is quasi-CMOS (n- and p-type materials are transferred separately, not monolithic), wafer-scale residue-free transfer at production throughput is unsolved, low-resistance contacts need fab-compatibility validation, and reliability data is limited. TSMC and imec place 2D channels on their roadmaps beyond 2030, with industry timelines targeting 2D logic as early as 2034 at the 0.7nm node.

For process engineers tracking gate scaling, this result confirms EUV single-patterning is sufficient for 50nm CPP and resolves a longstanding contact-engineering problem. The 2030+ deployment target means this is a long-term risk-reduction milestone, not an imminent production node. The broader significance: complementary FETs (CFETs) at 2nm (coming ~2033) will be the immediate next step; 2D channels are the subsequent frontier.