<cite index="54-4">TSMC raised its full-year capex target to $60 billion to $64 billion, a dramatic step up from the prior range of $52 billion to $56 billion and well above the $58 billion consensus. That implies second-half spending of $33.2 billion to $37.2 billion, a year-over-year surge of 56% to 75%.</cite> CEO C.C. Wei said <cite index="56-3">continued strong demand for leading-edge process technologies, including the steep ramp-up of 2-nanometer technology</cite> is driving the increase. <cite index="54-1">The company raised its full-year revenue growth target to above 40%</cite>, though gross margins guide to 65-67% due to 2nm ramp costs.
<cite index="54-4">CoWoS capacity has emerged as the true chokepoint in the AI supply chain. TSMC controls more than 90% of global CoWoS output, and current monthly capacity of roughly 90,000 wafers is expected to reach 120,000 by year-end. Nvidia alone has reportedly booked 60% of TSMC's CoWoS capacity through 2026, plus more than half of the expansion planned for 2026-2027.</cite> <cite index="54-2">The gap between CoWoS demand and available capacity could narrow from around 20% currently to roughly 10% by late 2026 as new production lines come online. If that timeline holds, hyperscale cloud providers could see reduced packaging delays in the second half of the year, accelerating the deployment of AI accelerators from Nvidia, AMD, and custom chip designers like Google, Amazon, and Microsoft.</cite>
For architects: TSMC's 2nm ramp is progressing, but advanced packaging—not leading-edge wafer fabs—is now the critical bottleneck. Chip-on-Wafer-on-Substrate (CoWoS) capacity at 90%+ utilization through Q3 2026 means AI accelerator delivery timelines are dictated by packaging, not die yields. Teams designing custom silicon or high-volume accelerator deployments should assume CoWoS lead times remain compressed through mid-2027.