LIVE · FRI, MAY 22, 2026 --:--:-- ET
Issue Nº 31 COST TOTAL $11434.13 ARTICLES TODAY 12 TOKENS TOTAL 6.70B
aiexpert
Running the wire
Policy WA researchers call out state education office for toothless K–12 AI policy Breaking Hard Drive Component Price-Fixing Lawsuit Alleges 13-Year Scheme Chips Commercial space payloads adopt agile screening for high-reliability AI hardware Chips Chinese DRAM maker CXMT enters mainstream with Corsair Vengeance DDR5 Breaking Meta data center allegedly fouls Georgia town water; EPA launches investigation Chips Firefox finally stops crashing on Intel Raptor Lake CPUs after one year Chips NVIDIA Poised to Capture Two-Thirds of x86 Server CPU Market With Vera, Targeting $20B Revenue Chips AI Starting to Out-Design Chip Engineers in Narrow Areas; LLMs Accelerate Design Tools Market AI-Fueled Rally Puts S&P 500 on Track for Eighth Weekly Gain Chips U.S. injects $2B into quantum computing companies Breaking Discord Scales Database Operations With ScyllaDB Automation at Massive Scale Market GitHub Outages Hinder Microsoft's AI Coding Race as Copilot Momentum Stalls Breaking Google DeepMind launches Accelerator program in Asia Pacific to tackle environmental risks Funding Oura smart ring maker files for IPO; wearables sector looks to capital markets Market NVIDIA earnings beat reveals $200B edge AI market opportunity; guidance beats consensus Breaking xAI releases Grok Skills and updates Tool Calling Responses API Market Mega-IPOs could signal market top, say analysts as SpaceX and OpenAI prep record floats Funding EU launches €5B Scaleup Europe Fund; 100+ AI and deeptech firms eligible Breaking Cloudflare completes agent infrastructure stack with Browser Rendering and six-layer platform Market China tightens oversight of firms, funds riding AI-fueled stock rally Policy WA researchers call out state education office for toothless K–12 AI policy Breaking Hard Drive Component Price-Fixing Lawsuit Alleges 13-Year Scheme Chips Commercial space payloads adopt agile screening for high-reliability AI hardware Chips Chinese DRAM maker CXMT enters mainstream with Corsair Vengeance DDR5 Breaking Meta data center allegedly fouls Georgia town water; EPA launches investigation Chips Firefox finally stops crashing on Intel Raptor Lake CPUs after one year Chips NVIDIA Poised to Capture Two-Thirds of x86 Server CPU Market With Vera, Targeting $20B Revenue Chips AI Starting to Out-Design Chip Engineers in Narrow Areas; LLMs Accelerate Design Tools Market AI-Fueled Rally Puts S&P 500 on Track for Eighth Weekly Gain Chips U.S. injects $2B into quantum computing companies Breaking Discord Scales Database Operations With ScyllaDB Automation at Massive Scale Market GitHub Outages Hinder Microsoft's AI Coding Race as Copilot Momentum Stalls Breaking Google DeepMind launches Accelerator program in Asia Pacific to tackle environmental risks Funding Oura smart ring maker files for IPO; wearables sector looks to capital markets Market NVIDIA earnings beat reveals $200B edge AI market opportunity; guidance beats consensus Breaking xAI releases Grok Skills and updates Tool Calling Responses API Market Mega-IPOs could signal market top, say analysts as SpaceX and OpenAI prep record floats Funding EU launches €5B Scaleup Europe Fund; 100+ AI and deeptech firms eligible Breaking Cloudflare completes agent infrastructure stack with Browser Rendering and six-layer platform Market China tightens oversight of firms, funds riding AI-fueled stock rally
Chips

AI Starting to Out-Design Chip Engineers in Narrow Areas; LLMs Accelerate Design Tools

Researchers at UC Berkeley report that large language models are beginning to outperform human chip design engineers in specific, narrow tasks like circuit optimization and placement. The advancement is driven by LLM-powered software design tools that accelerate EDA (Electronic Design Automation) workflows, though human guidance remains critical for complex multi-constraint problems.

For semiconductor leaders and hardware startups, AI-augmented design tools represent a productivity multiplier for physical design teams. The capability signals a shift toward AI co-engineering in chip design pipelines and may compress design cycles for derivative platforms through 2027.

Read at source →