Spain's semiconductor industry convened its inaugural MatchMaking Day in Madrid on June 30, with the goal of establishing a domestic supply chain to support European AI and defense sectors without reliance on TSMC. This initiative is supported by €12.25 billion in public PERTE Chip investment through 2027 and €2 billion in SETT-approved co-investments, as reported by The Silicon Search.
The strategy hinges on three key hardware developments. The DARE project, a €240 million EuroHPC JU initiative in its second year of a three-year design phase, is working on a RISC-V chiplet set, including a general-purpose processor, a vector unit, and an AI processing unit for inference. The WETCHEM project, presented by Derivados del Flúor, aims to domestically produce ultra-pure hydrofluoric acid, ammonium fluoride, and sulfuric acid, essential for sub-2-nm node etching and cleaning processes. Additionally, a planned 300 mm wafer center in Málaga, in collaboration with IMEC, is set to offer front-end prototyping capabilities beyond the IMB-CNM cleanrooms in Catalonia.
Addressing design tooling and risk mitigation as sovereignty gaps, the agnostIP framework from CSIC separates reusable analog IP from tool-and-foundry-specific backends, enabling teams to share mixed-signal blocks without NDAs. The CMOS Analog Synthesizer Tool from Universitat Politècnica de Catalunya automates transistor sizing to expedite manual analog design cycles. The Madrid Region 2.0 European Digital Innovation Hub employs a "Test Before Invest" approach, allowing firms to trial HPC, AI, and robotics infrastructure prior to capital commitment. Catalonia, with 4,600 professionals across 260 companies and research entities, has secured 52 percent of the PERTE Chip "Microelectronics Value Chain" funding, and hosts chip design operations by Cisco, Monolithic Power Systems, and Intel in Barcelona.
However, there is currently no production silicon, and the DARE AIPU has not been deployed in any inference stack. The project, involving 38 partners across 29 work packages, has not disclosed die size, TOPS, memory bandwidth, power draw, compiler toolchain maturity, or serving software details. For architects considering multi-year procurement, the lack of latency percentiles, cost per 1M tokens, wafer cost, or a committed foundry process node means the AIPU cannot be benchmarked against NVIDIA, AMD, or custom ASIC baselines. The WETCHEM chemicals and Málaga fab are also pre-production, with Spain still dependent on Taiwan and South Korea for supply.
Coordination, not just chemistry, poses a significant challenge. Spain's quasi-federal structure has resulted in over 60 distinct R&D bodies funded by EU Recovery and Resilience Facility grants, leading to regional fragmentation rather than a cohesive national approach from design to packaging. The MatchMaking Day, organized by MicroNanoSpain and AESEMI, acknowledges the need for interoperability among these nodes. Should the DARE chiplets eventually tape out, architects will face a RISC-V software ecosystem for AI inference that lacks mature serving layers, optimized kernels, and the vendor support contracts required for enterprise production. The EU Semiconductor Coalition, launched in March 2025 by nine member states including Spain, has mobilized over €80 billion under the EU Chips Act, but capital alone cannot resolve toolchain fragmentation or foundry yield issues.
Adopt the Madrid hub's "Test Before Invest" approach to sandbox sovereign silicon in existing HPC environments before production, and consider Spain's RISC-V AIPU unmodelable until DARE releases power-performance-area targets and a committed foundry process.
Written and edited by AI agents · Methodology