Meta's Iris AI chip enters production September; targets 14 gigawatts capacity by 2027
Meta will begin manufacturing its custom data center AI chip, code-named Iris, in September 2026 as part of its Meta Training and Inference Accelerators (MTIA) four-generation program, according to an internal memo reviewed by Reuters. The chip cleared six weeks of validation testing with no major design anomalies, signaling momentum for a program that floundered for over five years. Iris is optimized for Meta's recommendation algorithms (90% of daily AI workload), trades general compute for power efficiency, and will reduce reliance on third-party GPUs for inference. The chip was developed with Broadcom (physical design and interface architecture) and will be manufactured by TSMC.
The Iris strategy complements Meta's massive infrastructure expansion: 7 gigawatts deployed in 2026 (adding 1 GW in H1, another 5.5 GW by year-end), with plans to double to 14 gigawatts by 2027. Meta projects up to $145 billion in AI infrastructure spending this year alone—a major slice of Big Tech's $700 billion AI war chest. The company is also signing long-term supply deals with Samsung (memory), SanDisk (flash), and Sumitomo Electric (fiber-optic equipment) to protect against supply chain shocks and 'chipflation.' Meta plans to release new chips roughly every six months through 2027, versus the annual cycle typical in the industry.
Iris is explicitly positioned as an augmentation to, not replacement for, NVIDIA and AMD GPUs already purchased at scale by Meta. However, custom silicon allows Meta to deploy on its own schedule, cut per-unit inference costs, and reduce reliance on competitor pricing decisions—a control dimension that matters when Google can cap API usage (as it did to Meta's Gemini). The memo candidly admits integrating latest commercial GPUs 'has been a heavy lift, and it has cost us time,' signaling executive frustration with GPU supply constraints.
Why architects care: Meta's cadence (6-month chip releases, 14 GW target, $145B spend) accelerates the 'silicon sovereignty' race among hyperscalers. If custom Iris clears production and meets power-efficiency targets, the model pressures other cloud and AI labs to replicate custom-silicon strategies. This also signals that inference, not training, is the power/cost bottleneck driving ASIC design priorities—a contrast to 2024's GPU arms race and a validation of SambaNova and other inference-focused accelerator vendors.