Imec, ASML, TSMC Crack 50nm Pitch for 2D Transistors

Imec, ASML, and TSMC demonstrated complementary 2D-material transistors on a standard 300mm wafer at a 50nm contacted poly pitch (CPP) this week — the tightest pitch ever shown for complementary 2D devices and narrower than the 54nm CPP of Intel's 10nm-class silicon node. The work was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits. The n-channel devices use molybdenum disulfide (MoS2); the p-channel devices use tungsten diselenide (WSe2) or tungsten disulfide (WS2). Both polarities on a single wafer at node-relevant dimensions represents a first on a 300mm fab-compatible flow.

The lithography is standard. Channel lengths down to 28nm were printed with a single exposure on a 0.33-NA EUV scanner—no High-NA tooling, no multi-patterning. ASML credits sharper EUV resolution for collapsing channel lengths that prior 300mm 2D demonstrations had left bloated due to older optical tools. The 50nm CPP integrates gate length and source/drain contact length; earlier 2D work kept contact area large to manage resistance, which killed pitch scaling. Merging both constraints in a single EUV step moved the needle.

The team solved the contact problem by inverting the build sequence. Standard flow deposits metal onto the 2D film after channel formation, which pins the Fermi level at the junction, raises the Schottky barrier, and throttles current. The consortium instead patterned tungsten-filled contact trenches first, then transferred the 2D channel on top, with the gate deposited last. Imec calls this a "reverse" thin-film-transistor flow. Both polarities switch off cleanly at zero gate voltage—the off-state behavior that had been the persistent weak link on the p-type side. WSe2 pFETs landed close to the best lab-scale results reported to date.

Yield across the demonstrated arrays hit 94%, with an on/off current ratio above 100,000. Active widths ran down to 75nm with an equivalent oxide thickness near 2nm. These metrics place the demonstration inside the performance envelope of leading-edge silicon nodes by most primary measures. TSMC VP and CTO Min Cao framed the consortium's goal as de-risking the lab-to-fab transition for novel channel materials—a signal this is now a foundry-tracked workstream, not pure research.

Several hard problems remain. The current integration is quasi-CMOS: n- and p-type films are transferred onto the wafer side by side, not grown together in a single monolithic flow. Wafer-scale residue-free transfer at production throughput is unsolved. Fab-compatible low-resistance contacts, controllable doping without damaging the atomically thin channel, and long-term reliability data remain open. Intel runs a parallel 300mm 2D-material program with Imec; Samsung has demonstrated wafer-scale single-crystal MoS2 growth. The field is advancing, but no one has solved the transfer-yield problem.

Imec's published roadmap places 2D atomic channels beyond 2030, with complementary FETs (CFETs) expected around 2033 and the switch to 2D semiconductor channels for high-performance logic closer to 2041. The IRDS industry roadmap places 2D channels as early as 2034 at the 0.7nm node. TSMC only entered volume production on its first gate-all-around node, N2, late last year; the 2D generation sits at least two architecture transitions away from high-performance logic insertion. Near-term insertion is more likely in BEOL or wafer-backside devices where thermal and process constraints are looser.

For architects drawing compute roadmaps past 2028: the 50nm CPP result closes the integration gap that kept 2D transistors as a whiteboard option. The fab process path now exists. The remaining risk is yield at transfer—and that's a process engineering problem with a known owner.