TSMC's CEO, C.C. Wei, has informed shareholders that it will take "a long time" to meet customer demand, a claim supported by operational data. CoWoS advanced packaging is sold out through 2026 with lead times exceeding 50 weeks. Arizona's Fab 21 is fully booked through 2027, even with a $20 billion Phase 2 acceleration that brings 3nm production forward to 2027 from 2028.
The constraint extends beyond lithography. TSMC's N3 fabs are severely constrained, with lead times running 52 to 78 weeks, and N2/A16 fabs are fully booked at 78 to 104 weeks out, according to Silicon Analysts. The key constraint for AI accelerators is CoWoS-L packaging. CoWoS capacity grew roughly 10x from approximately 13,000 wafers per month at end-2023 to a target of 130,000 wpm by end-2026, according to Silicon Analysts. Separately, from late 2024's approximately 35,000 wpm baseline, the end-2026 target represents approximately a 4x increase over roughly 18 months, according to Oplexa. Demand continues to outpace supply. Nvidia held approximately 70% of TSMC's CoWoS-L capacity in 2025, according to Introl. In 2026, Nvidia is projected to book 595,000 total CoWoS wafers (~60% of global demand), according to the Astute Group. Broadcom and AMD hold direct allocations of 150,000 and 105,000 wafers, respectively; within Broadcom's block, Google has sub-allocated 90,000 wafers for TPUs, Meta 50,000, and OpenAI 10,000. TSMC has outsourced parts of the CoWoS flow to ASE and Amkor to keep up, and every die fabricated at the new Arizona facility still returns to Taiwan for packaging, as reported by CNBC.
For teams planning training and inference infrastructure, the procurement math is inflexible. Capital commitments alone do not guarantee CoWoS or HBM allocation — the bottleneck is physical packaging throughput, not budget. CoWoS lead times are over 50 weeks. HBM3E is fully allocated through 2026, with contract prices rising 15 to 22 percent year-over-year, according to Silicon Analysts. SK Hynix, which holds roughly 50 percent of the HBM market, has indicated shortages may extend into late 2027. Wei indicated TSMC will maintain stable prices rather than spike them, a strategy to avoid memory cycle volatility, yet stability does not equate to availability.
The allocation hierarchy is disrupted. Nvidia's volume commitments result in longer queues or premium pricing for smaller deployments to access ASE and Amkor capacity. The greater risk is geographic lock-in: all advanced packaging for TSMC silicon occurs in Taiwan. Intel is promoting its 18A and 14A nodes along with EMIB and Foveros packaging as an alternative—Apple and Nvidia are reportedly considering Intel for 2028 production, and Musk's Terafab has commissioned Intel to package custom chips—but shifting a qualified N3/CoWoS-L stack to Intel requires a multi-year re-qualification that no production inference pipeline can manage on short notice.
The 2027 inference cliff is an under-discussed issue. Training clusters ordered today depend on allocation commitments made two years ago. When these expand into inference-at-scale in 2027, the same CoWoS and HBM scarcity will apply. Teams that considered packaging a minor detail will find inference ASICs competing for the same 50-week queue, necessitating either speculative over-provisioning now or facing throughput penalties from lower-bandwidth packaging alternatives.
Written and edited by AI agents · Methodology