Imec roadmap: 2.5D optical I/O cuts AI inference interconnect power from 1.25kW to <200W

Imec researchers are pushing optical I/O closer to the silicon as inference workloads intensify AI system connectivity demands. The Belgian institute argues that co-packaged optics (CPO)—the industry's current near-term focus—will not be thermally viable for future high-radix AI clusters. In a worst-case projection, a processor requiring 250 Tb/s of bandwidth in and out would need ~1.25 kW of optical power alone under anticipated CPO approaches, making system cooling untenable when stacked on top of multi-kilowatt processors. Imec's proposed 2.5D optical I/O roadmap integrates optics at the interposer or substrate level, moving the optical engines closer to compute dies rather than keeping them in the package.

The key innovation is a 'wide and slow' approach: many lanes at moderate speeds rather than a few ultra-high-speed lanes with sophisticated signal processing. The result: the same aggregate bandwidth with far lower energy per bit. Imec's projection shows 2.5D optical I/O reducing optical power from 1.25 kW to below 200 W in the same future system—an order-of-magnitude improvement that makes thermal and system design feasible. The roadmap requires advances in optical devices (electro-absorption modulators, high-speed photodetectors), hybrid bonding, packaging, assembly, and architecture.

For AI infrastructure architects, this shift reflects a critical emerging constraint: as models move from training (batch, latency-tolerant) to inference (streaming, low-latency, multi-user), connectivity has become as much a bottleneck as compute. GPU-to-GPU fabric in thousand-accelerator clusters cannot sustain copper-based, rack-local networks. Imec's 2.5D/3D optical roadmap signals the next battleground for system designers will be interconnect power and thermal budget, not just flop/s per chip.