SiPearl Rhea CPU enters bring-up; Europe's first HPC processor on track for end-2026
SiPearl has received first silicon samples of its Rhea HPC CPU from TSMC and entered the 12-week bring-up process, with the company confirming the first samples work exactly as designed and require no respins. General availability is targeted for end of 2026. The Rhea1 CPU features 80 Arm Neoverse V1 cores with 1 MB L2 per core, 80 MB system-level cache, 61 billion transistors on TSMC's N6 process, and a unique hybrid memory subsystem: four HBM2E interfaces with 64 GB on-package capacity, plus four DDR5 interfaces supporting up to 2 TB of DRAM per socket.
The chip represents Europe's first sovereign HPC CPU and opens the door to addressing geopolitical supply-chain concerns. SiPearl has embedded five development teams across France (Maisons-Laffitte, Massy, Grenoble, Sofia Antipolis) and Spain (Barcelona), with a Bologna team in formation. The company aims to shorten future development cycles to 18 months. After bring-up, test silicon will be available to EU collaborative projects and partners at end of the process before commercial GA.
For architects, SiPearl's success signals a viable third path for HPC workloads beyond US-centric chip designs. The Rhea1 is already drawing interest from sovereign AI programs and European cloud providers seeking alternatives to American hardware amid export-control tensions. While the Neoverse V1 cores arrive late to market, the hybrid memory subsystem and on-premises deployment model position it for differentiated adoption in regulated sectors and European supercomputers. SiPearl expects to tape out Rhea2 (its second-generation processor without on-package HBM) in 2027, making Rhea1 a limited-run beachhead.