CXMT projected to match Micron's DRAM capacity by end-2026 at 350K wafers/month
Chinese memory maker ChangXin Memory Technologies (CXMT) is forecast to produce approximately 350,000 DRAM wafers per month by the end of 2026, nearly matching Micron's expected 375,000 wafers per month, according to Citrini Research's bottom-up capacity model. If realized, this would position CXMT as the fourth-largest global DRAM producer (by wafer capacity), reshaping competitive dynamics in the commodity memory market and signaling China's rapid ascent in semiconductor self-sufficiency.
The government is reportedly directing CXMT to share its DRAM technology with peers JHICC, Swaysure, and YMTC subsidiary XMC to ease domestic shortages. If all these facilities reach planned capacity in coming years, China's total DRAM output would reach 600,000 wafers per month by the end of the decade—significantly lower than South Korea but ahead of Japan, Taiwan, and the US combined. CXMT itself is targeting 950,000 WSPM by 2030 through new fabs in Beijing, Hefei, and Shanghai. The company is also ramping HBM3 production, starting volume production in 2026.
For operators: CXMT's capacity gain does not immediately translate to market displacement. While the company has shipped DDR5 at 8,000 MT/s with densities approaching competitors, yields, product mix, and supply-chain maturity still lag the incumbents. The real constraint is advanced lithography—US export controls block CXMT from EUV tools, forcing reliance on older DUV equipment and multi-patterning. Domestic tools (SMEE, SiCarrier) may ramp by 2027, but production maturity is not expected before the early 2030s. The key watch: global DRAM demand is forecast to exceed supply through at least 2027, meaning CXMT's incremental capacity feeds existing shortage rather than crushing prices short-term.
Sources
- Primary source
- tomshardware.com
“CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron”
- newsletter.semianalysis.com
“By the end of 2026, we expect CXMT to reach roughly 350 kwspm, which is only modestly below Micron's estimated ~385 kwspm”
- cloudnews.tech
“translating that capacity into more bits per wafer, advancing in DDR5 and LPDDR, producing competitive HBM yields, and doing so without full access to the most advanced tools”