Rapidus targets 2nm wafer pricing 25–35% below TSMC, aims for 2027 HVM launch

Japanese chipmaker Rapidus announced aggressive pricing for its 2nm-class process technology, targeting ¥3–3.5 million ($18,550–$21,635) per wafer—roughly 30–40% below TSMC's rumored N2 quote of ~$30,000 and competitive with Samsung's SF2 at $20,000. The move signals Rapidus' strategy to lure customers away from Taiwan's foundry leader by combining lower costs with single-wafer processing that accelerates production cycles, though the company will lack TSMC's mature Open Innovation Platform (OIP) ecosystem of design tools, IPs, and packaging services.

Rapidus plans to start high-volume manufacturing (HVM) at its IIM-1 fab in the second half of 2027, with meaningful volume arriving in 2028 once yield learning completes. By then, TSMC will have shipped N2P and begun ramping the more advanced N2X node, along with the mature supply-chain advantages it has accumulated. The company is negotiating with 60+ potential customers, mostly overseas.

For architects evaluating foundry lock-in and cost: Rapidus' pricing is substantive but risky. The single-fab model and inexperience with gate-all-around yield processes mean early customers will absorb learning curves and supply-constrain risk. However, if Rapidus executes even partially, it signals permanent price pressure on foundry rates—TSMC's N2 margin floor is higher than the $18k–22k Rapidus is targeting. Watch supply agreements announced in H2 2026 and H1 2027 as the real signal of market confidence.