SK hynix & TetraMem demo memristor edge-AI chip, 21.3 TOPS/W efficiency for lightweight inference

<cite index="55-2">TetraMem Inc. and SK hynix announced the successful completion of a joint technology collaboration, highlighted by the publication of their research paper "A Memristor-based In-Memory Computing SoC with Efficient Depthwise Convolution" in Advanced Intelligent Systems, also selected as the journal's cover feature</cite>. <cite index="54-2">The device is designed to accelerate neural network inference in lightweight AI models while consuming a fraction of the power that higher-end GPUs or NPUs would</cite>.

<cite index="54-2">The SoC peaks at around 2.54 TOPS in a theoretical best-case scenario, which is 16X below Microsoft's Copilot+ requirements</cite>. However, <cite index="54-3">the SoC delivers a peak throughput of 0.254 TOPS per NPU and reaches an energy efficiency of 21.3 TOPS/W at 100 MHz and 11.9 TOPS/W at 400 MHz, exceeding Nvidia's A100 INT8 energy efficiency by an order of magnitude</cite>. The chip operates on a 65nm process and uses 10 neural processing units, with one dedicated to depthwise convolution optimization.

The architecture combines memristor-based in-memory computing (IMC) with SK hynix fabrication expertise. <cite index="54-3">TetraMem replaced conventional crossbars with zig-zag topology, enabling 28 independent 3×3 convolutions to run in parallel while using 100% of the array for weight storage</cite>. The design targets edge inference for models like MobileNet, addressing the challenge of moving AI computation closer to data while reducing power draw—a critical constraint for IoT and edge devices.

For practitioners: this is a proof-of-concept demonstration of memory-centric computing, not a shipping product. The theoretical 2.54 TOPS limit and 65nm process suggest limited near-term commercial viability for large-scale deployments. However, the journal-cover publication and vendor collaboration signal growing R&D investment in in-memory architectures as the industry explores alternatives to conventional GPU/NPU designs for specific edge workloads. The energy efficiency claim (21.3 TOPS/W) is meaningful for battery-constrained devices if manufacturing scales.