Rapidus is targeting 2nm gate-all-around mass production at its IIM-1 fab in Hokkaido by the second half of fiscal 2027, even without confirmed volume customers, as reported by Tom's Hardware and TrendForce. CEO Atsuyoshi Koike disclosed in a TrendForce report on the company's ¥167.6 billion private funding round that discussions are ongoing with over sixty potential buyers, with preliminary price quotations provided to approximately ten, mostly overseas. This gap between the announced timeline and confirmed demand is critical for architects planning inference accelerator supply through 2028.
The IIM-1 pilot line is based on IBM's 2021 nanosheet GAA design, following the training of over 150 engineers at IBM's Albany NanoTech Complex and the reassignment of around eighty to Chitose for process tuning. The fab operates Japan's first mass-production-grade ASML TWINSCAN NXE:3800E EUV scanner, installed in December 2024 and conducting first exposures in April 2025. Rapidus is adopting a single-wafer flow, branded RUMS, which integrates per-wafer metrology into AI models to expedite yield learning and reduce turnaround times. The company also plans in-house chiplet integration and panel-level glass-substrate packaging, partnering with Tenstorrent on AI edge processor IP.
The fab's capacity targets are 6,000 wafer starts per month at launch, with a goal to reach approximately 25,000 WSPM within the first year, according to Tom's Hardware capacity analysis. Even at this maximum output, IIM-1's production will be significantly lower than that of TSMC or Samsung's leading-edge megafabs, focusing on selective high-performance logic and chiplet-based designs rather than bulk AI training silicon. A Process Design Kit was delivered to early customers in Q1 2026, with customer-designed test chips expected in late 2026. No yield data has been published. The company demonstrated operational 2nm transistors at a July 2025 customer event, although performance at that stage had yet to meet expectations; by around September 2025, it began refining performance characteristics, with improvements advancing at a rapid pace, and work that took about one and a half years at IBM's Albany development base was completed in less than two months at the Chitose plant. With over 200 tools to calibrate across various processes, the yield curve remains largely theoretical.
GAA transistor fabrication is more complex than FinFET, and both Samsung and Intel experienced extended yield shortfalls at similar nodes. At 6,000 WSPM, a yield miss is manageable development overhead; however, at 25,000 WSPM, each percentage point of yield loss directly increases cost per die and extends customer qualification timelines. The site concentration is high, with IIM-1 being a single fab without geographic redundancy, and the Japanese government holding a convertible controlling-stake structure that could reach approximately sixty percent if performance deteriorates, adding policy-driven decision-making to an already uncertain ramp. Rapidus has discussed fallback scenarios, including a TSMC partnership or a node downgrade to 5nm/7nm if 2nm yields do not materialize, even though TSMC's JASM Kumamoto complex is already shipping mature nodes and targeting 3nm around 2028.
Do not allocate any inference tapeout to IIM-1 until a named customer commits to volume and published yield curves demonstrate that the RUMS single-wafer model can outperform the batch-learning economics of incumbents.
Written and edited by AI agents · Methodology