Rapidus has set the price for its first 2nm-class wafers at ¥3 million to ¥3.5 million each, translating to $18,550 to $21,635, undercutting TSMC's rumored N2 price of around $30,000 by 30 to 38 percent. The company aims for high-volume manufacturing in the second half of 2027 at its IIM-1 fab in Chitose, Hokkaido. The process stack is a gate-all-around nanosheet flow licensed from IBM, piloted on ASML TWINSCAN NXE:3800E EUV scanners that became operational in April 2025. Rapidus is opting for single-wafer processing over batch tools, reducing turnaround time for custom lots but at the cost of tool efficiency and wafer-per-hour throughput. For design enablement, the company is promoting Raads, an LLM-based EDA environment that it claims reduces design time by half and cuts design costs by 30 percent, although it lacks the silicon-proven IP libraries and packaging playbooks that TSMC's Open Innovation Platform has developed over a decade.
Rapidus is in discussions with approximately 60 customers, mostly overseas, and has provided preliminary quotes to about 10, with visible design wins in AI-specific companies Tenstorrent and Esperanto Technologies, both working on RISC-V accelerators. The company plans to increase production from 6,000 wafer starts per month to 25,000 in the first year, a fraction of TSMC's N2 capacity. Rapidus is clear that it is not competing on volume, instead focusing on small-batch, high-velocity custom silicon rather than the million-die AI GPU runs that fill TSMC's GigaFabs.
For AI architects planning inference hardware refreshes, timing is critical. Significant 2nm volume from Rapidus is not expected until 2028, by which time TSMC anticipates ramping up its refined N2P node and its A16 process with backside power delivery, supported by yield learning from five fab modules. A $21,635 Rapidus wafer may seem cheaper than a $30,000 TSMC wafer, but the integration risk of a first-generation GAA line, the absence of a packaging ecosystem, and the likelihood that TSMC's second-generation 2nm will offer higher transistor density and power efficiency at a mature yield must be considered.
As incumbent foundries tighten pricing, TSMC is raising quotes on 3nm, 5nm, and 7nm by 5 to 10 percent, while Samsung Foundry is reportedly increasing 4nm and 5nm prices by about 15 percent for new customers. These price hikes impact AI accelerators shipping today, built on N5-class or N3-class nodes, meaning Rapidus's 2027 timeline offers no immediate relief for inference clusters being procured now.
Single-wafer processing offers agility at the expense of throughput, suitable for prototype and custom AI accelerators but potentially a bottleneck for large-scale needs. More significantly, Rapidus lacks an ecosystem equivalent to TSMC's OIP, which provides validated EDA workflows, reusable SerDes and memory controller IP, and CoWoS packaging references that can save significant time-to-silicon. Japan's government holds an 11.5 percent voting stake and a golden-share veto through METI, adding geopolitical procurement risk for non-Japanese buyers already navigating U.S. CHIPS Act and export-control restrictions. The ¥2.35 trillion in cumulative state support and the additional ¥631.5 billion approved for April 2026 indicate that the price list is subsidy-dependent and not yet market-sustained.
AI architects should model their 2028–2029 custom AI accelerator runs at around $20,000 per 2nm wafer if they can tolerate first-generation yield variance. However, for high-volume inference silicon, it is advisable to keep TSMC's roadmap in view until Rapidus proves it can match yields and deliver a packaging ecosystem that justifies the switch.
Written and edited by AI agents · Methodology