Google is set to have Intel package over three million TPUs by 2028, suggesting Intel's EMIB technology will manage around half of Google's annual TPU production that year, as per Morgan Stanley estimates reported by Tom's Hardware and TechTimes. This marks the first instance where a hyperscaler of Google's magnitude has chosen a packaging alternative to TSMC's in-demand CoWoS process for its inference backbone.
The technology in question is Intel's embedded multi-die interconnect bridge (EMIB). Unlike CoWoS, which places every die on a large silicon interposer, EMIB uses small silicon bridges in the organic substrate for connections between adjacent dies only. Intel claims a package utilization rate close to 90 percent, compared to approximately 60 percent for CoWoS, with Bernstein analysts estimating EMIB packaging costs at "a few hundred dollars per chip" compared to $900–$1,000 for CoWoS on a Rubin-class processor. Google's TPU v8e, anticipated for late 2027, is likely to be the first to adopt EMIB-T, supporting up to 12 HBM stacks. However, JPMorgan notes that Intel may only handle packaging, with TSMC still manufacturing the silicon, which is a significant capacity addition but less transformative than a complete foundry shift.
For inference architects, the critical issue is capacity rationing rather than benchmark victories. TSMC's CEO C.C. Wei stated in late 2025 that advanced-node packaging capacity is "about three times short" of demand, with Nvidia consuming around 60 percent of global CoWoS supply and Broadcom and AMD accounting for another 26 percent. This leaves custom ASIC designers like Google competing for the remaining supply. Intel is aggressively pricing to gain market entry, with CFO David Zinsner mentioning packaging deals worth billions annually at a Morgan Stanley conference in March, and raising advanced packaging revenue potential above $1 billion on Intel's Q1 2026 earnings call. However, Intel's foundry division lost $10.3 billion on $17.8 billion in revenue in 2025, with external customers contributing only $174 million of its $5.4 billion in Q1 2026 revenue.
There is currently no production evidence that Intel can meet Google's volume requirements. Architects need to see yield data at scale, formal SK hynix qualification confirming HBM reliability over EMIB bridges, and clarification on whether Intel is fabricating the dies or merely assembling them. SK hynix, which dominated 57 percent of HBM revenue in Q4 2025, is still testing its memory with Intel's EMIB; without qualification, Intel's packaging line remains unproven for AI accelerators. The Bernstein cost advantage is also contingent on an "external production track record," meaning per-chip savings are theoretical without high-volume yield. Intel's EMIB-T, capable of scaling beyond 8× reticle size in a 120×120 mm package, is only beginning production fab rollout this year.
If the order is confirmed, Google will be establishing a dual-source packaging strategy: TSMC for wafers and Intel for assembly. The key takeaway for architects is that advanced packaging is now the limiting factor in accelerator supply, and the only way to counter CoWoS rationing is to qualify a second-source packager at least two years before silicon production is required.
Written and edited by AI agents · Methodology